MIKROE nvSRAM Click is a compact add-on board that contains the most reliable nonvolatile memory. This board features the CY14B101J, a 1-Mbit nvSRAM organized as 128K words of 8 bits each with a nonvolatile element in each memory cell from Cypress Semiconductor. The embedded nonvolatile elements incorporate the QuantumTrap technology and provide highly reliable nonvolatile storage of data. Data transfer, initiated by the user through I2C commands, from SRAM to the nonvolatile elements takes place automatically at Power-Down. On the other hand, during the Power-Up, data is restored to the SRAM from the nonvolatile memory. This Click board™ is suitable for all applications that require fast access and high reliability of stored data, and unlimited endurance.
nvSRAM Click is based on the CY14B101J, a 1-Mbit nvSRAM organized as 128K words of 8 bits each with a nonvolatile element in each memory cell from Cypress Semiconductor. The CY14B101J integrates an SRAM cell and a nonvolatile memory cell into a single nvSRAM cell. In the Normal mode, all reads and writes happen directly from and to the SRAM portion of the nvSRAM. This provides faster write and read access compared to any existing nonvolatile memory technology such as EEPROM and Flash.
The nvSRAM specifies one million endurance cycles for nonvolatile cells with data retention of a minimum of 20 years. In the event of system power loss, data from the SRAM is transferred to its nonvolatile cell automatically by using energy stored in a capacitor labeled as C2. During the Power-Up, data from the nonvolatile cell is recalled automatically in the SRAM array and available to the user. The endurance cycle is consumed only when data transfer happens from the SRAM cells to nonvolatile cells during the Power-Down.
nvSRAM Click communicates with MCU using the standard I2C 2-Wire interface with a clock frequency up to 100kHz in the Standard, up to 400kHz in the Fast, up to 1MHz in the FastPlus, and up to 3.4MHz in the High-Speed Mode. The CY14B101J offers zero cycle delay write operation with infinite SRAM write endurance. Besides, it also allows the choice of the least significant bit (LSB) of its I2C peripheral address by positioning SMD jumpers labeled as ADDR SEL to an appropriate position marked as 0 and 1.
An additional feature of this Click board™ represents the configurable Write Protection function labeled as WP routed on the PWM pin of the mikroBUS™ socket. The WP pin is an active-high pin that protects the entire memory and all registers from write operations. This pin must be held high to inhibit all the write operations. When this pin is high, all memory and register writes are prohibited, and the address counter is not incremented.
This Click board™ is designed to be operated only with a 3.3V logic voltage level. A proper logic voltage level conversion should be performed before the Click board™ is used with MCUs with different logic levels.
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