Flash 2 Click features a 64 Mbit Flash memory IC, manufactured by using the proprietary high-performance CMOS Super-Flash® technology, which allows the Flash 2 Click to withstand up to 100,000 write cycles, with the data retention period of 100 years, which is considerably longer than any other memory module of this type. The flash memory IC used on this Click board™ features Serial Flash Discoverable Parameters (SFDP) mode, used to retrieve the advanced information from the device, such as the operating characteristics, structure and vendor specified information, memory size, operating voltage, timing information, and more.
Featuring high data transfer speed via the SPI interface, the improved reliability of the stored information, one time programmable (OTP) memory block, write protect and suspend, this Click board™ can be used as a mass storage option in multimedia devices, data drives, non-volatile data storage in embedded applications, and similar applications that require reliable permanent storage of data blocks. Addition of 2 KB of one-time programmable (OTP) memory can be useful for building secure storage devices and similar secure storage applications.
The Flash memory module used on this Click board™ is the SST26VF064B, a 64 Mbit serial Flash memory, from Microchip. The Flash memory density is usually expressed in bits, so exactly 67,108,864 bits are organized in units of 8 bits (bytes), which gives 8,388,608 bytes of data memory. This memory module contains 2048 sectors of 4 KB each. Furthermore, the memory is organized in pages. One page holds 256 bytes and there are 32,768 pages (32,768 pages x 256 bytes = 8,388,608 bytes total). Having insight into how the memory cells are organized, is very important for understanding the Write and Erase operations. The SST26VF064B communication consists of sending the instruction from the host MCU via the SPI interface, followed by either an address, data, or both. The SPI interface pins are routed to the mikroBUS™ so the interfacing with the microcontroller unit (MCU) is easy and straightforward. Additional pins routed to the mikroBUS™ include the #WP pin routed to the mikroBUS™ PWM pin, labeled as WP, and #HOLD pin routed to the mikroBUS™ RST pin, labeled as HLD.
The SST26VF064B offers a flexible memory protection scheme that allows each individual block to be write-protected. In addition, the Write Protection Lock-Down register prevents any change of the lock status during device operation. To simplify the operation, there is a Global Block Protection Unlock command, which unlocks the entire memory array at once. Finally, the one-time programmable register (OTP) can be used to permanently lock the Block Protection bits, preventing any further changes to the individual protected blocks of data.
The #WP write protect pin is used to put the device into the hardware write protect mode. A LOW logic level on this pin prohibits write operations to the Block-Protection and Configuration registers. Locking down the Status Register will block changes of the WEN bit, which is required for the Write and Erase operations, effectively preventing the memory content changes. The Write Protect Enable (WPEN) non-volatile bit is used to control the function of the #WP pin: if set to 0, the #WP pin function is disabled.
The #HOLD pin is used to hold the data transfer. When the chip select pin (#CS, routed to the mikroBUS™ CS pin) is set to a LOW logic level, the data transfer will be put on hold when the LOW logic level of the serial clock coincides with the falling edge of the #HOLD pin. Similarly, resuming the data transfer will happen when the LOW logic level of the serial clock coincides with the rising edge of the #HOLD pin.
Both of the #WP and #HOLD pins will be disabled if the I/O reconfiguration bit (IOC) is set by the EQIO command. This command sets these pin to additional serial data outs while working in Quad SPI mode.
Besides the standard SPI mode, SST26VF064B also supports the SQI (Quad SPI) data transfer, which can be enabled by sending the command from the host controller. While in SQI mode, the internal multiplexer will reconfigure the IC pins as four Serial Data Output pins, so that the #WP pin becomes SO2, #HOLD Pin becomes SO3, SO pin becomes SO1, and SI pin becomes SO0. To resume the normal operation, the device needs to receive the SQI reset command, which will revert all the pins to their defaults. Due to a small number of MCUs that support SQI, MikroElektronika offers library functions which work only with the standard SPI communication, ensuring the absolute compatibility with all the supported MCUs.
Before attempting any write operations to the flash memory, the Write Enable bit (WEL) of the Status Register needs to be set to 1. This bit is automatically set to 0 after some instructions, as well as during the Write operation itself, preventing accidental damage to the memory content. There are special instructions used to set and clear the WEN bit of the Status Register. Usually, every write operation will be prefixed with the WREN instruction.
Page Program instruction (0x02) allows up to 256 bytes to be written during one write cycle. After the initial command, three more address bytes are sent, followed by the data that needs to be written. It is possible to write less than 256 bytes, which will be written at the starting address, not affecting the rest of the data on the same page. After successful write cycle, the state of the Write in Progress (WIP) bit is set to 0 automatically, and the device is ready to accept another erase or write instruction. Therefore, the status register can be polled for the status of the WIP bit, in order to shorten the wait time for the next operation
Data can be read by the Read Data Bytes instruction (0x03). This instruction is followed by an address, from which the data is shifted to the output register and read by the host MCU. The address increment is automatically executed, making it possible to read the entire memory by a single Read Data command. HIGH logic level on the chip select pin (CS) will terminate the operation.
An interesting fact is that Page Program instruction can only reset the bits to 0. Therefore, a segment of memory needs to be erased prior to programming, or in this case - filled with 1s (0xFF). The SST26VF064B IC allows erasure of one sector at a time (Sector Erase instruction, 0x20), block at a time (Block Erase instruction, 0xD8), and the entire memory (using the Chip Erase instruction, 0x60). The same mechanism applies here too: polling the WIP bit helps to shorten the wait for the total time for the next operation.
There is 2 KB of OTP memory, which can be used to store various security data. Once programmed, this memory can be permanently locked, without a possibility to reprogram it ever again. The Program Security ID instruction (0xA5) is used to program the OTP memory locations. The same principle as Page Program applies here too, except only two address bytes are sent, followed by the data to be written.
SST26VF064B features Serial Flash Discoverable Parameters (SFDP) mode. Host MCU can retrieve the operating characteristics, structure and vendor specified information such as identifying information, memory size, operating voltage and timing information of this device by sending the SFDP Read command. This will initiate cyclic transfer from the SFDP memory table, which can be stopped at any moment by driving the chip select pin (CS) to a HIGH logic level.
For the detailed commands explanation and more in-depth information, please consult the included datasheet. However, MikroElektronika provides a library which contains functions that simplify and speed up working with this device. The provided application example demonstrates the functionality of the library functions. It can be used as a reference for a custom project development.
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